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Publications
Books
  1. J. B. O. Souza Filho, Lan-Da Van, T. P. Jung and P. S. R. Diniz, Online Component Analysis, Architectures and Applications. Foundations and Trends in Signal Processing, vol. 16, issue 3-4, pp. 224-429, now publishers, 2022. (ISBN 978-1-63828-116-0)

  2. Lan-Da Van, Editor, Intel Atom Platform: Intelligent Systems Development and Applications. Library & Book, 2014. (in Traditional Chinese, Sponsored by Intel, ISBN 978-986-90988-3-0)

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Journal Papers
  1. A. Mukashev, Lan-Da Van, S. Sharma, M. F. Tandia, and Y. C. Tseng, "Person tracking by fusing posture data from UAV video and wearable sensors," IEEE Sensors Journal, vol. 22, no. 24, pp. 24150-24160, Dec. 15, 2022. [PDF]

  2. Lan-Da Van, Y. C. Tu, C, Y. Chang, H. J. Wang, and T. P. Jung, "Hardware-oriented memory-limited online artifact subspace reconstruction (HMO-ASR) algorithm," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 12, pp. 3493-3497, Dec. 2021. [PDF]

  3. Lan-Da Van, L. Y. Zhang, C. H. Chang, K. L. Tong, K. R. Wu, and Y. C. Tseng, "Things in the air: Tagging wearable IoT information on drone videos," Discover Internet of Things, vol. 1, issue 1, Feb. 2021. [PDF]

  4. Lan-Da Van, Y. B. Lin, T. H. Wu, and Y. C. Lin, "An intelligent elevator development and management system," IEEE Systems Journal, vol. 14, no. 2, pp. 3015-3026, Jun. 2020. [PDF]

  5. Lan-Da Van, Y. B. Lin, T. H. Wu, and T. H. Chao, "Green elevator scheduling based on IoT communications," IEEE Access, vol. 8, pp. 38404-38415, Mar. 2020. [PDF]

  6. Lan-Da Van, Y. B. Lin, T. H. Wu, S. H. Peng, L. H. Kao, and C. H. Chang, "PlantTalk: A smartphone-based intelligent hydroponic plant box," Sensors, vol. 19, issue 8, Apr. 2019. [PDF]

  7. Lan-Da Van, I. H. Khoo, P. Y. Chen, and H. C. Reddy, "Symmetry incorporated cost-effective architectures for two-dimensional digital filters," IEEE Circuits and Systems Magazine, vol. 19, no. 1, pp. 33-54, Q1, 2019. [PDF]

  8. C. C. Chiu, Lan-Da Van, and Y. S. Lin, "Efficient progressive radiance estimation engine architecture and implementation for progressive photon mapping," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 8, pp. 2491-2502, Aug. 2018. [PDF]

  9. Lan-Da Van, P. Y. Huang, and T. C. Lu, "Cost-effective and variable-channel FastICA hardware architecture and implementation for EEG signal processing," Journal of Signal Processing Systems, vol. 82, issue 1, pp. 91-113, Jan. 2016. [PDF]

  10. I. H. Khoo, H. C. Reddy, Lan-Da Van, and C. T. Lin, "General formulation of shift and delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the symmetry," Multidimensional Systems and Signal Processing, vol. 25, issue 4, pp. 795-828, Oct. 2014. [PDF]

  11. Lan-Da Van, D. Y. Wu, and C. S. Chen, "Energy-efficient FastICA Implementation for biomedical signal separation," IEEE Transactions on Neural Networks, vol. 22, no. 11, pp. 1809-1822, Nov. 2011. [PDF]

  12. Lan-Da Van , and T. Y. Sheu, "A power-area efficient geometry engine with low-complexity subdivision algorithm for 3D graphics system," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, no. 9, pp. 2211-2224, Sep. 2011. [PDF]

  13. D. Y. Wu and Lan-Da Van, "Efficient detection algorithms for MIMO communication systems," Journal of Signal Processing Systems, vol. 62, issue 3, pp. 427-442, Mar. 2011. [PDF]

  14. P. Y. Chen, Lan-Da Van, I. H. Khoo, H. C. Reddy, C. T. Lin, "Power-efficient and cost-effective 2-D symmetry filter architectures," IEEE Transactions on Circuits and Systems I, vol. 58, no. 1, pp. 112-125, Jan. 2011. [PDF]

  15. J. H. Tu and Lan-Da Van, "Power-efficient pipelined reconfigurable fixed-width Baugh-Wooley multipliers," IEEE Transactions on Computers, vol. 58, no. 10, pp. 1346-1355, Oct. 2009. [PDF]

  16. C. T. Lin, Y. C. Yu, and Lan-Da Van, "Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor," IEEE Transactions on VLSI Systems, vol. 16, no. 8, pp. 1058-1071, Aug. 2008. [PDF]

  17. Lan-Da Van, C. T. Lin, and Y. C. Yu, VLSI architecture for the low-computation cycle and power-efficient recursive DFT/IDFT design," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 8, pp. 1644-1652, Aug. 2007. [PDF]

  18. M. A. Song, Lan-Da Van, and S. Y. Kuo, "Adaptive low-error fixed-width Booth multipliers," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 6, pp. 1180-1187, Jun. 2007. [PDF]

  19. Lan-Da Van and C. C. Yang, “Generalized low-error area-efficient fixed-width multipliers,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, pp. 1608-1619, Aug. 2005. [PDF]

  20. Lan-Da Van, "A new 2-D systolic digital filter architecture without global broadcast," IEEE Transactions on VLSI Systems, vol. 10, pp. 477-486, Aug. 2002. [PDF]

  21. Lan-Da Van and W. S. Feng, "An efficient systolic architecture for the DLMS adaptive filter and its applications," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, pp. 359-366, April 2001. [PDF]

  22. Lan-Da Van, S. S. Wang, and W. S. Feng, "Design of the lower error fixed-width multiplier and its application", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, pp. 1112-1118, Oct. 2000. [PDF]
International Conference Papers
  1. G. S. Wang, C. Y. Lin, Y. C. Tseng, and Lan-Da Van, "A multilayer perceptron model for station grouping in IEEE 802.11ah networks," in Proc. IEEE/IFIP Network Operations and Management Symposium (NOMS), Dec. 2023, pp. 1-5, May, Miami, FL, USA, accepted. [PDF]

  2. A. B. Christian, Y. H. Wu, C. Y. Lin, Lan-Da Van, and Y. C. Tseng, "Radar and camera fusion for object forecasting in driving scenarios," in Proc. IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Dec. 2022, pp. 105-111, Penang, Malaysia. (Hybrid Conference). [PDF]

  3. A. B. Christian, C. Y. Lin, Y. C. Tseng, Lan-Da Van, W. H. Hu, and C. H. Yu, "Accuracy-time efficient hyperparameter optimization using actor-critic-based reinforcement learning and early stopping in OpenAI Gym environment," in Proc. IEEE International Conference on Internet of Things and Intelligence Systems (IoTaIS), Nov. 2022, pp. 230-234, Bali, Indonesia. (Hybrid Conference) [PDF]

  4. R. Ali, I. S. Hutomo, Lan-Da Van, and Y. C. Tseng, "A skeleton-based view-invariant framework for human fall detection in an elevator," in Proc. IEEE International Conference on Industrial Technology (ICIT), Aug. 2022, pp. 1-6, Shanghai, China. (Hybrid Conference) [PDF]

  5. Lan-Da Van, T. J. Wang, S. J. Tzeng, and T. P. Jung, "A computation-aware TPL utilization procedure for parallelizing the FastICA algorithm on a multi-core CPU," in Proc. IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Dec. 2021, pp. 171-177, Singapore. (Hybrid Conference) [PDF]

  6. A. B. Christian, C. Y. Lin, Lan-Da Van, and Y. C. Tseng, "Data fusion driven lane-level precision data transmission for V2X road applications," in Proc. IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Dec. 2021, pp. 157-163, Singapore. (Hybrid Conference) [PDF]

  7. T. A. Huang, S. K. Wong, and Lan-Da Van, "Trajectory-based dynamic handwriting recognition using fusion neural network," in Proc. International Conference on Technologies and Applications of Artificial Intelligence (TAAI), Nov. 2021, pp. 7-12, Taichung, Taiwan. [PDF]

  8. S. Sharma, A. V. V. Susmitha, Lan-Da Van, and Y. C. Tseng, "An edge-controlled outdoor autonomous UAV for colorwise safety helmet detection and counting of workers in construction sites," in Proc. IEEE Vehicular Technology Conference (VTC-Fall), Sep. 2021, pp. 1-5. (Virtual Conference) [PDF]

  9. A. B. Christian, C. Y. Lin, C. W. Lee, Lan-Da Van, and Y. C. Tseng, "A neural network-based multisensor data fusion approach for enabling situational awareness of vehicles," in Proc. International Conference on Pervasive Artificial Intelligence (ICPAI), Dec. 2020, pp. 199-205, Taipei, Taiwan. [PDF]

  10. Lan-Da Van, C. H. Chang, K. L. Tong, K. R. Wu, L. Y. Zhang, and Y. C. Tseng, "Demo: Tagging IoT data in a drone view," in Proc. ACM Annual International Conference on Mobil Computing and Networking (MobiCom), Oct. 2019, Los Cabos, Mexico. [PDF]

  11. Lan-Da Van, T. C. Lu, T. P. Jung, and J. F. Wang, "Hardware-oriented memory-limited online FastICA algorithm and hardware architecture for signal separation," in Proc. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), May 2019, pp. 1438-1422, Brighton, UK. [PDF]

  12. T. C. Lu, C. L. Lin, P. Y. Chen, and Lan-Da Van, "FPGA-oriented real-time EMD-based breath signal processing system on ARM11 MPCore platform," in Proc. IEEE International Conference on Diginal Signal Processing (DSP), Nov. 2018, pp. 1-4, Shanghai, China. [PDF]

  13. Lan-Da Van, T. C. Lu, P. Y. Chen, and H. C. Reddy, "Type-4 2-D diagonal and four-fold rotational symmetry digital filter architectures," in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Oct. 2018, pp. 115-118, Chengdo, China. [PDF]

  14. Z. Z. Wu, C. W. Wu, Lan-Da Van, and Y. C. Tseng, "Qnalyzer: Queuing recognition using accelerometer and Wi-Fi signals," in Proc. IEEE Global Communications Conference (GLOBECOM), Dec. 2017, pp. 1-7, Singapore. . [PDF]

  15. P. Y. Chen, Lan-Da Van, H. C. Reddy, and I. H. Khoo, "Type-3 2-D multimode IIR filter architecture and the corresponding symmetry filter's error analysis," in Proc. IEEE International Conference on ASIC (ASICON), Oct. 2017, pp. 726-729, Guiyang, China. [PDF]

  16. P. Y. Chen, Lan-Da Van, I. H. Khoo, and H. C. Reddy, "New 2-D quadrantal- and diagonal-symmetry filter architectures using delta operator," in Proc. IEEE International Conference on ASIC (ASICON), Oct. 2017, pp. 1133-1136, Guiyang, China. [PDF]

  17. P. Y. Chen, Lan-Da Van, H. C. Reddy, and I. H. Khoo, "New 2-D filter architectures with quadrantal symmetry and octagonal symmetry and their error analysis," in Proc. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2017, pp. 265-268, Boston, MA, USA. [PDF]

  18. X. Zhang, C. W. Wu, P. Fournier-Viger, Lan-Da Van, and Y. C. Tseng, "Analyzing students' attention in class using wearable devices," in Proc. IEEE International Symposium on a World of Wireless, Mobile and Multimedia Networks (WoWMoM), Jun. 2017, pp. 1-9, Macau, China. [PDF]

  19. T. H. Wu, C. H. Chang, Y. W. Lin, Lan-Da Van, and Y. B. Lin, "Intelligent plant care hydroponic box using IoTtalk," in Proc. IEEE International Conference on Internet of Things (iThings) and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, Physical and Social Computing (CPSCom) and IEEE Smart Data (SmartData), Dec. 2016, pp. 398-401, Chengdu, China. [PDF]

  20. T. C. Lu, P. Y. Chen, S. W. Yeh, and Lan-Da Van, "Multiple stopping criteria and high-precision EMD architecture implementation for Hilbert-Huang transform," in Proc. IEEE Biomedical Circuits and Systems Conference (BioCAS), Oct. 2014, pp. 200-203, Lausanne, Switzerland. [PDF]

  21. J. W. Qiu, T. H. Chiang, C. C. Lo, L. M. Lin, Lan-Da Van, Y. C. Tseng, and Y. T. Ching, "Continuous human location and posture tracking by multiple depth sensors," in Proc. IEEE International Conference on Internet of Things (iThings), and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, Physical and Social Computing (CPSCom), Sep. 2014, pp. 155-160, Taipei, Taiwan. [Best Paper Award] [PDF]

  22. T. C. Lu, S. H. Hsu, S. J. Tzeng, C. M. Chang, and Lan-Da Van, "Implementation of a human-centric GUI for next-generation intensive care unit," in Proc. IEEE International Conference on Consumer Electronics-Taiwan, May 2014, pp. 179-180, Taipei, Taiwan. [PDF]

  23. P. Y. Chen, Lan-Da Van, H. C. Reddy, and I. H. Khoo, "Area-efficient 2-D digital filter architectures possessing diagonal and four-fold rotational symmetries," in Proc. International Conference on Information, Communications and Signal Processing (ICICS), Dec. 2013, pp. 1-5, Tainan, Taiwan. [PDF]

  24. I. H. Khoo, H. C. Reddy, Lan-Da Van, and C. T. Lin, "Design of 2-D digital filters with almost quadrantal symmetric magnitude response without 1-D separable denominator factor constraint," in Proc. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2013, pp. 999-1002, OH, USA. [PDF]

  25. I. H. Khoo, H. C. Reddy, Lan-Da Van, and C. T. Lin, "Delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the quadrantal symmetry," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2012, pp. 3190-3193, Seoul, Korea. [PDF]

  26. T. C. Lu, Lan-Da Van, C. S. Lin, and C. M. Huang, "A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/conversion-step SAR ADC for biomedical applications,"in Proc. IEEE Custom Integrated Circuits Conference (CICC), Sep. 2011, pp. 1-4, CA, USA. [PDF]

  27. I. H. Khoo, H. C. Reddy, Lan-Da Van, and C. T. Lin, "Generalized formulation of 2-D filter structures without global broadcast for VLSI implementation," in Proc. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2010, pp. 426-429, Seattle, WA, USA. [PDF]

  28. P. Y. Chen, Lan-Da Van, and H. C. Reddy, and C. T. Lin, "A new VLSI 2-D fourfold-rotational-symmetry filter architecture design," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2009, pp. 93-96, Taipei, Taiwan. [PDF]

  29. I. H. Khoo, H. C. Reddy, Lan-Da Van, and C. T. Lin, "2-D digital filter architectures without global broadcast and some symmetry applications," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2009, pp. 952-955, Taipei, Taiwan. [PDF]

  30. T. Y. Sheu, Lan-Da Van, T. R. Jung, C. W. Lin, and T. W. Chang, "Low complexity subdivision algorithm to approximate Phong shading using forward difference," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2009, pp. 2373-2376, Taipei, Taiwan. [PDF]

  31. L. Y. Lin, H. K. Lin, C. Y. Wang, Lan-Da Van, and J. Y. Jou, "Hierarchical architecture for network-on-chip platform, in Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2009, pp. 343-346, Hsinchu, Taiwan. [PDF]

  32. W. C. Huang, S. H. Hung, J. F. Chung, M. H. Chang,Lan-Da Van, and C. T. Lin, "FPGA implementation of 4-Channel ICA for on-line EEG signal separation," in Proc. IEEE Biomedical Circuits and Systems Conference (BioCAS), Nov. 2008, pp. 65-68, Baltimore, MD, USA. [PDF]

  33. P. Y. Chen,Lan-Da Van, and H. C. Reddy, and C. T. Lin, "A new VLSI 2-D diagonal-symmetry filter architecture design," in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2008, pp. 320-323, Macao, China. [PDF]

  34. D. Y. Wu and Lan-Da Van, "A grouped-iterative framework for MIMO detection," in Proc. IEEE Vehicle Technology Conference (VTC), Sep. 2008, pp. 1-5, Calgary, BC, Canada. [PDF]

  35. T. R. Jung, T. Y. Sheu, C. W. Lin, Lan-Da Van, and W. C. Fang, "Design of multi-mode depth buffer compression for 3D graphics system," in Proc. IEEE International Conference on Multimedia and Expo (ICME), Jun. 2008, pp. 789-792, Hannover, Germany. [PDF]

  36. C. W. Hsueh, J. F. Chung, Lan-Da Van, and C. T. Lin, "Anticipatory access pipeline design for phased cache," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2008, pp. 2342-2345, Seattle, WA, USA. [PDF]

  37. C. C. Huang, S. H. Hung, J. F. Chung, Lan-Da Van, and C. T. Lin, "Front-end amplifier of low-noise and tunable BW/Gain for portable biomedical signal acquisition," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2008, pp. 2717-2720, Seattle, WA, USA. [PDF]

  38. T. R. Jung, Lan-Da Van, W. C. Fang, and T. Y. Sheu, "Reconfigurable depth buffer compression design for 3D graphics system," in Proc. International Conference on Multimedia and Ubiquitous Engineering, Apr. 2008, pp. 470-474, Busan, Korea. [PDF]

  39. C. T. Lin, L. W. Ko, K. L. Lin, B. C. Kuo, S. F. Liang,I. F. Chung, and Lan-Da Van, "Classification of driver's cognitive responses using nonparametric single-trial EEG analysis," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2007, pp. 2019-2023, New Orleans, LA, USA. [PDF]

  40. C. M. Huang, K. J. Lee, C. C. Yang, W. S. Hu, S. S. Wang, J. B. Chen, C. S. Chen, Lan-Da Van, C. M. Wu, W. C. Tsai, and J. Y. Jou,, "Multi-Project System-on-Chip (MP-SoC): A novel test vehicle for SoC silicon prototyping," in Proc. IEEE International System-on-Chip Conference (SOCC), Sep. 2006, pp. 137-140, TX, USA. (Invited Paper) [PDF]

  41. Lan-Da Van, H. F. Luo, N. H. Chang, and C. M. Huang, "A cost-effective reconfigurable accelerator for platform-based SOC design," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2006, pp. 1977-1980, Island of Kos, Greece. [PDF]

  42. C. T. Lin, Y. C. Yu, and Lan-Da Van, "A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2006, pp. 4523-4526, Island of Kos, Greece. [PDF]

  43. Lan-Da Van, Y. C. Yu, C. M. Huang, and C. T. Lin, "Low computation cycle and high speed recursive DFT/IDFT: VLSI algorithm and architecture," in Proc. IEEE Workshop on Signal Processing Systems (SiPS), Nov. 2005, pp. 579-584, Athens, Greece. [PDF]

  44. H. Y. Chao, J. S. Wang, C. M. Wu, C. M. Huang, and Lan-Da Van, "High-performance low-complexity bit-plane coding scheme for MPEG-4 FGS," in Proc. IEEE International Conference on Multimedia and Expo (ICME), Jul. 2005, Amsterdam, Netherlands. [PDF]

  45. Y. C. Fan, Lan-Da Van, C. M. Huang, and H. W. Tsao, "Hardware-efficient architecture design of wavelet-based adaptive visible watermarking," in Proc. IEEE International Symposium on Consume Electronics (ISCE), Jun. 2005, pp. 399-403, Macau, China. [PDF]

  46. M. A. Song, Lan-Da Van, C. C. Yang, S. C. Chiu, and S. Y. Kuo, "A framework for the design of error-aware power-efficient fixed-width Booth multipliers," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2005, pp. 81-84, Kobe, Japan. [PDF]

  47. C. A. Tsai, Y. T. Chou, Y. T. Chang, Lan-Da Van, and C. M. Huang, "ARM-based SoC prototyping platform using Aptix," in Prof. ICEER, Mar. 2005, Tainan, Taiwan. [Best Poster Award] [PDF]

  48. M. A. Song, Lan-Da Van, T. C. Huang, and S. Y. Kuo, "A generalized methodology for low-error and area-time efficient fixed-width Booth multipliers", IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Jul. 2004, vol. 1, pp. 9-12, Hiroshima, Japan. [Best Student Paper Nomination] [PDF]

  49. Lan-Da Van, H. F. Luo, C. M. Wu, W. S. Hu, C. M. Huang, and W. C. Tsai, "A high-performance area-aware DSP processor architecture for video codecs," in Proc. IEEE International Conference on Multimedia and Expo (ICME), Jun. 2004, pp. 1499-1502, Taipei, Taiwan. [PDF]

  50. Lan-Da Van and C. C. Yang, "High-speed area-efficient recursive DFT/IDFT architectures," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2004, vol. 3, pp. 357-360, Vancouver, BC, Canada. [PDF]

  51. M. A. Song, Lan-Da Van, T. C. Huang, and S. Y. Kuo, "A low-error and area-time efficient fixed-width Booth multiplier," in Proc. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Dec. 2003, vol. 2, pp. 590-593, Cairo, Egypt. [PDF]

  52. Lan-Da Van and C. H. Chang, "Pipelined RLS adaptive architecture using relaxed Givens rotations (RGR)," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2002, vol. 1, pp. 37-40, Phoenix-Scottsdale, AZ, USA. [PDF]

  53. Lan-Da Van and S. H. Lee, "A generalized methodology for lower-error area-efficient fixed-width multipliers," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2002, vol. 1, pp. 65-68, Phoenix-Scottsdale, AZ, USA. [PDF]

  54. C. C. Tang, W. S. Lu, Lan-Da Van, and W. S. Feng, "A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2001, vol. 4, pp. 794-797, Sydney, NSW, Australia . [PDF]

  55. Lan-Da Van and W. S. Feng, "Efficient systolic architectures for 1-D and 2-D DLMS adaptive digital filters," in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Dec. 2000, pp. 399-402, Tianjin, China. [PDF]

  56. Lan-Da Van, S. Tenqchen, C. H. Chang, and W. S. Feng, "A new 2-D digital filter using a locally broadcast scheme and its cascade form," in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Dec. 2000, pp. 579-582, Tianjin, China. [PDF]

  57. Lan-Da Van, C. C. Tang, S. Tenqchen, and W. S. Feng, "A new VLSI architecture without global broadcast for 2-D systolic digital filters ," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 2000, vol. 1, pp. 547-550, Geneva, Switzerland. [PDF]

  58. Lan-Da Van, S. S. Wang, S. Tenqchen, W. S. Feng, and B. S. Jeng, "Design of a lower error fixed-width multiplier for speech processing application," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), May 1999, vol. 3, pp. 130-133, Orlando, FL, USA. [PDF]

  59. Lan-Da Van, S. Tenqchen, C. H. Chang, and W. S. Feng, "A tree-systolic array of DLMS adaptive filter," in Proc. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Mar. 1999, vol. 3, pp. 1253-1256, Phoenix, AZ, USA. [PDF]
Patents
  1. C. M. Huang, C. C. Yang, J. Y. Jou,, K. J. Lee, and Lan-Da Van, "Multi-project system-on-chip and its method", US Patent, No: 7,571,414 B2 Aug. 2009.

  2. 黃俊銘、楊智喬、周景揚、李昆忠、范倫達, "多計畫系統單晶片平台及其設計方法", ROC Patent, No: I306211, Feb. 2009.
Dissertation and Thesis
  1. Lan-Da Van, Design of Efficient VLSI Architectures: Multiplier, 2-D Digital Filter, and Adaptive Digital Filter, Ph. D. Dissertation, Dept. of the Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., Jun. 2001.

  2. Lan-Da Van, New Architectures and Implementations of FIR Filters Using Efficient Multipliers, Master Thesis, Dept. of the Electrical Engineering, Tatung Institute of Technology, Taipei, Taiwan, R.O.C., Jun. 1997.
Articles (In Traditional Chinese)
  1. 范倫達、林進燈, "參加2008年『大學優良教師傳承』研討會之我思", 交大有聲, 431期, pp. 66-66, Dec. 2008. [This session is orgainzed by 國立交通大學 許炳堅 榮譽教授]

  2. 許藤耀、林丞蔚、鍾宗融、張庭維、涂晉豪、范倫達, "3D圖學渲染演算法之簡介與研究", 影像與識別, vol.14, no. 2, pp. 61-69, 2008.

  3. 黃俊銘、楊智喬、胡文祥、王旭昇、陳正斌、陳麒旭、吳建明、范倫達、周景揚, "計畫系統單晶片(Multi-Project System-on-Chip, MP-SoC)介紹", 電子月刊, pp. 116-127, May, 2007.
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